New Seminar: Signal Integrity Considerations in the Design of Super Ultra Speed PCBs 29-12-25

Join us for an exclusive New Technology Seminar on December 29, 2025
 

New technology particularly entails the use of high speed digital circuits, responding to the need for increased processing rates of data.

As system operating frequencies are increasing, PCB layout is becoming increasingly complex. A successful ultra-high-speed PCB must effectively integrate high speed ASIC’s and other components to optimize signal integrity. Device interfaces utilizing fast I/O pins and with edge rates that are less than a hundred picoseconds introduce a particular concern. Since fast edge rates can contribute to noise generation, signal reflection, crosstalk and ground bounce; designers must be careful to handle these issues during PCB layout.

This one-day comprehensive Seminar addresses the fundamental methods for controlling and satisfying signal integrity concerns.

The Seminar highlights the primary topics related to the discipline of ultra-fast PCB SI, which the designer may encounter, including PCB materials, power integrity, data-buses and clock propagation, high speed memory (DDR2, DDR3) interfaces, and transmission line effects, ultra-high speed differential signaling, etc.network with peers from the industry. 

Seats are limited – reserve your spot today and take your power supply design knowledge to the next level.